.TH ASMLINE 1 2022-01-21 GNU

.SH NAME
asmline \- assemblyline tool 

.SH SYNOPSIS
.B asmline
[OPTIONS]...
path/to/file.asm

.SH DESCRIPTION
.B asmline 
Generates machine code from a file or stdin containing x86_64 assembly instructions. Machine code could be directly executed without the need for an executable file format. 

.SH OPTIONS

.TP
.BR \-r[=LEN] ", " \-\-return[=LEN]
Assembles given code. Then executes it with six parameters to heap-allocated memory. Each pointer points to an array of LEN 64-bit elements which can be dereferenced in the asm-code, where LEN defaults to 10. After execution, it prints out the contents of the return (rax) register and frees the heap-memory.

.TP
.BR \-\-rand
Implies -r and will additionally initialize the memory from with random data. 
.br
-r=11 can be used to alter LEN.

.TP
.BR \-p ", " \-\-print
The corresponding machine code will be printed to stdout in hex form. Output is similar to `objdump`: Byte-wise delimited by space and linebreaks after 7 bytes. If-c is given, the chunks are delimited by '|' with each chunk on one line.

.TP
.BR \-P ", " \-\-printfile " " \fIFILENAME
The corresponding machine code will be printed to \fIFILENAME\fR in binary form. Can be set to '/dev/stdout' to write to stdout.

.TP
.BR \-c ", " \-\-chunk " " \fICHUNK_SIZE>1
Sets a given \fICHUNK_SIZE\fR boundary in bytes. Nop padding will be used to ensure no instruction opcode will cross the specified \fICHUNK_SIZE\fR boundary.

.TP
.BR \-b ", " \-\-breaks " " \fICHUNK_BOUNDARY>1

Given a \fICHUNK_BOUNDARY\fR asmline will count the number of instructions where their opcode crosses the specified \fICHUNK_BOUNDARY\fR size in bytes.

.TP
.BR \-o ", " \-\-object " " \fIFILENAME
Generates a binary file from path/to/file.asm called \fIFILENAME\fR.bin in the current directory.

.TP
.BR \-\-nasm\-mov\-imm
Enables nasm-style mov-immediate register-size handling. where if immediate size for mov is less than or equal to max signed 32-bit assemblyline  will emit code to mov to 32-bit register rather than 64-bit.
.br
\fBThat is:\fR "mov rax, 0x7fffffff" as "mov eax, 0x7fffffff" -> b8 ff ff ff 7f
.br
\fBNOTE:\fR rax got optimized to eax for faster immediate to register transfer and produces a shorter instruction.

.TP
.BR \-\-strict\-mov\-imm
Enables strict mov-imm thereby disabling nasm-style mov-immediate register-size handling.
.br
\fBex:\fR even if immediate size for mov is less than or equal to max signed 32-bit
.br
    assemblyline will pad the immediate to fit 64bit.
.br
\fBThat is:\fR "mov rax,0x7fffffff" as "mov rax,0x000000007fffffff" 
.br
          -> 48 b8 ff ff ff 7f 00 00 00 00

.TP
.BR \-\-smart\-mov\-imm
Assemblyline will check the immediate value for leading 0's and thus allows manual optimizations. Immediate must be zero padded to 64-bits exactly to ensure it will not optimize. This is currently set as default.
.br
\fBex:\fR "mov rax, 0x000000007fffffff" -> 48 b8 ff ff ff 7f 00 00 00 00
.br
    "mov rax, 0x7fffffff" -> b8 ff ff ff 7f


.TP
.BR \-\-nasm\-sib\-index\-base\-swap
In SIB addressing if the index register is esp or rsp then the base and index registers will be swapped as this is because the stack pointer register is not scalable in SIB. This is currently set as default.
.br
\fBThat is:\fR "lea r15, [rax+rsp]" interpreted as "lea r15, [rsp+rax]"
.br
         -> 4c 8d 3c 04
.br
         "lea r15, [rsp+rsp]" will produce an error because 
.br
         base and index cannot be swapped)

.TP
.BR \-\-strict\-sib\-index\-base\-swap
In SIB addressing the base and index registers will not be swapped even if the index register is esp or rsp.
.br
\fBThat is:\fR "lea r15, [rax+rsp]" will be interpreted as "lea r15, [rax+riz]"
.br
         -> 4c 8d 3c 20
.br
\fBNOTE:\fR riz is a pseudo-register evaluated by GCC to constant 0 and therefore cannot be used in assemblyline as a string ie. assembling "lea r15, [rax+riz]" is invalid "lea r15, [rsp+rsp]" will produce an error (invalid instruction)


.TP
.BR \-\-nasm\-sib\-no\-base
In SIB addressing if there is no base register present and scale is equal to 2; the base register will be set to the index register and the scale will be reduced to 1.
.br
\fBThat is:\fR "lea r15, [2*rax]" -> "lea r15, [rax+1*rax]"
.br
         -> 4c 8d 3c 00

.TP
.BR \-\-strict\-sib\-no\-base
In SIB addressing when there is no base register present the index and scale would not change regardless of scale value.
.br
\fBThat is:\fR "lea r15, [2*rax]" -> "lea r15, [2*rax]"
.br
         -> 4c 8d 3c 45 00 00 00 00

.TP
.BR \-\-nasm\-sib
Equivalent to \fB--nasm-sib-no-base\fR \fB--nasm-sib-index-base-swap\fR.
.br

.TP
.BR \-\-strict\-sib
Equivalent to \fB--strict-sib-no-base\fR \fB--strict-sib-index-base-swap\fR.
.br

.TP
.BR \-n ", " \-\-nasm
Equivalent to \fB--nasm-mov-imm\fR \fB--nasm-sib-index-base-swap\fR \fB--nasm-sib-no-base\fR.
.br

.TP
.BR \-t ", " \-\-strict
Equivalent to \fB--strict-mov-imm\fR \fB--strict-sib-index-base-swap\fR \fB--strict-sib-index-base-swap\fR.

.TP
.BR \-s ", " \-\-smart
Equivalent to \fB--smart-mov-imm\fR.
.br 

.TP
.BR \-h ", " \-\-help
Prints usage information to stdout and exits.
.TP
.BR \-v ", " \-\-version
Prints version information to stdout and exits.

.SH SEE ALSO
.B libassemblyline(3)